There is a constant demand for increase of data storage capacity in digital systems. This results in the continuous development of methods to increase bit density in magnetic recording systems. As bit density increases, data are packed more tightly on tracks, the distance between adjacent magnetization transitions diminishes and intersymbol interference, nonlinear distortions and noise, caused by interference from the neighboring tracks, increase. Partial Response Maximum Likelihood (PRML) detection has become an established and effective method of restoring read-back signals to the form of their original digital signals.
A block diagram of a prior art data storage write-read system, based on magnetic recording and partial response maximum likelihood detection, is shown in FIG. 1.
With the device of FIG. 1., during a write operation, user data, containing a preamble in the beginning, are applied to the input of a storage device. A run length limited (RLL) encoder 10 performs a mapping of the unconstrained user data to a RLL constrained sequence, where the number of zeros between two successive ones is bounded from above as well as from below. A precoder 11 converts the received binary sequence into a new sequence in order to compensate for the transfer function of a write/read head assembly together with preamplifiers and equalizer. A write precompensation unit 12 modifies the exact timing of reversals of the write current depending on how far away the previous and upcoming transitions are with respect to each other. In that way, it provides a read-back pulse shape that best fits the particular decoding scheme being employed. The obtained sequence of binary bits is written to a magnetic disk media 15 through a write head 14.
During a read operation, the read head 16 reads back data from the magnetic disk 15. The read channel preamplifiers 100, that include gain control, raise the level of the read-back signals, making possible their subsequent processing. A low pass filter (LPF) 101 suppresses high frequency noise and cuts off the read-back signal spectrum, preventing aliasing during further analog to digital conversion in an analog-to-digital converter (ADC) 102. A high pass filter (HPF) 103 suppresses low frequency noise in the read-back signal, principally the interference from neighboring tracks. An equalizer 104 corrects the frequency response of the write/read channel and shapes the waveform of the read-back signal according to a desired form of the “target” response which is necessary for effective operation of Viterbi detector 106. Samples of read-back signal at the output of ADC 102 appear with a frequency that is higher than the frequency of data bits: during each time interval occupied by one bit more than one sample appears. A clock recovery circuit 105 restores samples of the read-back signal in correct time positions, with exactly one sample per data bit. For that purpose, the clock recovery 105, among other things, carries out the initial clock frequency and phase acquisition by processing the preamble, which forms a part of read-back signal. After processing the preamble, clock recovery 105 performs tracking of the relatively slow instabilities of the rotational speed of the disk 15. Tracking is a process of phase error correction, with phase errors being usually calculated from differences between input signal samples and expected sample values known a priori. Viterbi detector 106 determines the sequence of data bits that best matches the input sequence of the read-back signal samples in spite of signal corruption by noise, interference and different distortions. The assembly of the equalizer, clock recovery and Viterbi detector constitutes a PRML receiver. The features and inner structure of the PRML receiver specify to a large extent the qualitative characteristics of the storage system, and principally the bit error rate (BER). An RLL decoder 107 transforms the detected data obtained from the Viterbi detector 106 output into user data to be presented at the storage device output. In the absence of errors, the user data at the output of the data storage device during the read operation, are the same as the user data applied to the device input during the write operation.
A block-diagram of a prior art Viterbi detector is shown in FIG. 2. That Viterbi detector constitutes a state machine, and comprises, in general, N states. In each state, the next bit may be 0 or 1. The Viterbi detector includes a set of 2N metric calculators 201-1 . . . 201-(2N−1). Each metric calculator computes an Euclidean error metric as the squared difference between the actual signal sample at the Viterbi detector input and an expected sample that is kept in corresponding one of 2N expected sample registers 200-0 . . . 200-(2N−1). The expected sample corresponding to a particular branch of a state transition diagram for the Viterbi detector; is supposed to appear at the Viterbi detector input, if that particular branch is to “survive.” When standard targets are used, then the expected samples for different branches often coincide. In such cases, corresponding expected sample registers and metric calculators may be united to simplify the apparatus. Sometimes, separate expected sample registers are not used, and instead, information about the expected sample is enclosed in the inner structure of an associated metric calculator. At each sample interval, computed metric is transferred from a metric calculator to a corresponding one of N add-compare-select units (ACS) 202-0 . . . 202-(N−1). Each ACS unit adds the new metric to the previously accumulated branch metric for each of its associated two branches. Then, the two accumulated branch metrics are compared, and the smaller is selected as the “surviving” branch metric for that state. The candidates for future bits of Viterbi detector output digital signal for each state are kept in candidate registers 204-0 . . . 204-(N−1). Each of the candidate registers has a bidirectional exchange input/output. The bidirectional exchange input/outputs of all candidate registers are united, providing the possibility of contents transfer between any two candidate registers. The outputs of the ACS units 202-0 . . . 202-(N−1) are connected to the inputs of registers controller 203. In response to the control signals applied to its inputs, the registers controller 203 shifts into each of the candidate registers 204-0 . . . 204-(N−1), the appropriate binary symbol corresponding to the selected branch (i.e., the branch that “survived”). Furthermore, the registers controller 203 merges the survivor candidate sequences, stored in candidates registers 204-0 . . . 204-(N−1), based on branches, that were eliminated. Eventually, all candidates are merged into one survivor sequence, so that all candidate registers contain the same bits at their respective outputs. The Viterbi detector output can be taken from the output of any one of the candidate registers. In FIG. 2 the output is taken from the last candidate register 204-(N−1).
The use of a PRML receiver of the conventional form solves most of the problem of linear intersymbol interference. However, there are several causes of high density recording performance quality degradation, that remain not resolved by prior art PRML receivers.
The equalizer 104 that is an obligatory part of the conventional PRML receiver, generally has a transfer function with a “boost” in the high frequency region. Since the noise level typically exceeds the read-back signal components at high frequencies, this boost causes a reduction in signal to noise ratio with a corresponding deterioration of the bit error rate (BER). Generally, an optimization procedure based on a least-mean-square algorithm, is used in the PRML receivers with the objective of finding a compromise between the noise level increase and residual signal distortions (see, for example, U.S. Pat. No. 5,995,544 “Adaptive equalization for PR IV transmission systems”). A somewhat different approach, with the goal to adjust the Viterbi detector threshold levels during the optimization procedure, is disclosed in U.S. Pat. No. 5,341,387 “Viterbi detector having adjustable detection thresholds for PRML class IV sampling data detection,” U.S. Pat. No. 5,440,433 “Circuit and method for adjusting a data detecting level of a disk driving apparatus,” U.S. Pat. No. 5,610,776 “Method of optimizing read channel of disk drive recording apparatus by using error rate,” and U.S. Pat. No. 5,954,837 “Method for optimizing Viterbi detector thresholds values.” An attempt to alleviate the equalizer optimization procedure by using more complicated response polynomial, is disclosed in U.S. Pat. No. 6,249,398 “Class of partial response targets in a PRML sampled data detection channel.” In U.S. Pat. No. 6,600,617 “Method and apparatus for adjusting digital filter taps based upon minimization of Viterbi margin counts,” the use of a Viterbi detector margin for equalizer optimization is disclosed. In spite of so numerous and various efforts, the problem cannot be considered to be settled conclusively. In the prior art, a significant part of the BER in magnetic recording storage systems is due to the presence of the equalizer in a PRML receiver.
As storage systems are developed with increased magnetic recording density, magnetiorestrictive (MR) heads are often used, leading to a sharp rise of nonlinear distortions in the read-back signal. When the distance between adjacent transitions on magnetic media decreases, a transition, that immediately follows a preceding transition, is subjected to magnetic interference from the preceding transition and is shifted toward that preceding transition. The distance between transitions becomes different from the ideal: the so-called nonlinear transition shift (NLTS) appears. Additional nonlinear distortions appear because of hysteresis in the magnetic material and hard transition shift. Correction of nonlinear distortions by refinements in the inner structure of Viterbi detector was suggested in U.S. Pat. No. 5,889,823 “Method and apparatus for compensation of linear or nonlinear intersymbol interference and noise correlation in magnetic recording channels,” and U.S. Pat. No. 6,393,598 “Branch metric compensation for digital sequence detection.” Write precompensation as a method to reduce the number of error caused by NLTS, was disclosed in U.S. Pat. No. 5,493,454 and U.S. Pat. No. 5,583,705 with the same title “Write precompensation optimization in a PRML channel using a selected PRML signal level.” Methods of nonlinearity correction and/or compensation, that are known today, are very useful and were crucial in enhancement of magnetic recording density. However even after they are applied, substantial nonlinear distortions remain in the read-back signal with corresponding detrimental effects.
A significant change in the conventional Viterbi detector was proposed in U.S. Pat. No. 5,588,011 “Tuned Viterbi detector and equalizer system”. It was suggested to compute branch metrics as squared differences between an input sample and a reference sample, with the reference sample being found as a result of averaging input samples related to a certain binary combination in the Viterbi detector output digital signal. Since such implementation eliminates the necessity of any assumptions about superposition of responses in the read-back signal, the Viterbi detector of this type becomes much more resistant to any nonlinear distortions. Unfortunately, the use of Viterbi detector output digital signal, while determining reference samples, and the absence of appropriate changes in clock recovery circuit, that would provide for phase correction with arbitrary pulse response shapes, make it compulsory to include an equalizer in the resultant PRML receiver, as it was before. An additional drawback of this prior art implementation of a Viterbi detector, is the compulsory coincidence between state length and the distance at which nonlinear distortions are corrected in a PR IV detector, for example, the state length is two bits, whereas nonlinear intersymbol interference may spread over 3, 4 and more bits, so that nonlinear distortions in the prior art PRML receiver, cannot be cleared out completely as a matter of principle.
Thus, a method and apparatus for PRML receiver implementation, that make possible its operation without read-back signal equalization and which prevents error occurrence due to nonlinear distortions with any nonlinear interference distance, would be an important improvement in the art.